Circuit Desi Intern in München bei Apple

Circuit Design Intern (m/f/d) in München bei Apple

Apple

Summary

Posted: Oct 13, 2023

Role Number: 200511472

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product. Do you love working on challenges that no one has solved yet? As a member of our dynamic group, you will have the unique and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. Imagine yourself at the center of our pioneering processor design in deep submicron technologies, and on standard cell library designs. You will drive concepts of transistor level circuit design, modelling and performance analysis, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will integrate and build new ideas, share insights and collaborate with a team of hardworking engineers.

Key Qualifications

Preliminary understanding of CMOS circuits, device characteristics and PPA oriented design
An understanding of layout design and how to drive PPA via parasitic optimization, in addition to SPICE simulators
Good proficiency in scripting languages like Perl, Python and Tcl
Excellent problem solving and analytical thinking skills
Collaboration skills and written and verbal communication in English

Description

As a Circuit Design Intern for the custom circuits, you will build your skills in the below areas: - Work on new cell architectures and optimization for PPA improvement - Analyse layout and identify parasitic reducing options to improve cell PPA - Be involved in technical discussions on new standard cell circuit development - Collaborate with different teams to ensure IP production and quality is met

Education & Experience

Currently enrolled in your penultimate year of studies in a CE, EE, CS or related field (or your final year for an internship which is required to complete your course).